1. Field of the Invention
The present invention relates, most generally, to methods for forming semiconductor structures and structures formed therefrom, and more particularly to methods for forming a die with a multi-layer interconnect structure and structures formed therefrom.
2. Description of the Related Art
With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed requirements, dimensions of semiconductor integrated circuits have been reduced and various materials, such as copper and ultra low-k dielectrics, have been proposed and are being used along with techniques for overcoming manufacturing obstacles associated with these materials and requirements. In order to achieve high-speed performance, dimensions of transistors have been shrinking. Also, multi-layer interconnect structures have been proposed and/or used to provide desired operational speeds of transistors.
FIG. 1 is a schematic cross-sectional view showing a traditional single die with a multi-layer interconnect structure.
Referring to FIG. 1, the single die 101 has a device 102 formed over a substrate 100. Dielectric layers 110, 130, 140 and 150 are sequentially formed over the substrate 100. Contacts/vias 109, 133, 143 and 153 are formed within the dielectric layers 110, 130, 140 and 150, respectively. Metallic layers 111, 135, 145 and 155 are formed over the dielectric layers 110, 130, 140 and 150, respectively. The contacts 109 contact source/ drain regions 107 of the device 102.
Different layers of the single die 101 are subjected to particles/defects contamination. Particles kill yields of wafers if they fall on different dies in different device layers or metallic layers. The issue becomes more serious when the number of metallic layers increases and the dimensions of devices and metallic layers shrink.
Based on the foregoing, methods and structures for forming dies with multi-layer interconnect structures are desired.